ur5beta.m

$INCLUDE ur5beta.ma

$CONT
$LIST
$LOC
$CONT_END

$PROG “UR-5beta Microprogram”
$INSERT |UR-5beta Microcode|

$set # = ‘C00′

; BRT, JA ['001'], XSRC, TST
“
Get Starting Macroprogram Counter (PC)
“
; MCPU, DICSRC, DICSC [CI], DICFC [RA]
; MCPU, DICSRC, DIC [0]
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [DZ], BR[15], BSRC
“
Get Starting Stack Pointer (SP)
“
; MCPU, DICSRC, DICSC [CI], DICFC [RA]
; MCPU, DICSRC, DIC [0]
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [DZ], BR[14], BSRC
“
Stop after single Macroinstruction
“
;:STRT DST [NOP]
“
Fetch OPC
“
; MCPU, DICSRC, DICSC [CM]
; MCPU, LDOC, FNC [&ADD], SRC [ZB], BR[15], BSRC “Latch LDOC”
; MCPU, DICSRC, DIC [0]
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; BRT, TST
; BRT, TST
“
Execute OPC
“
;:LLO_I MCPU, DICSRC, DICSC [CM].; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; DST [RAMF], FNC [&ADD], SRC [DZ], CC
; BRT, JA [STRT], XSRC, TST
;:MUV DST [RAMF], FNC [&ADD], SRC [ZA], CC
; BRT, JA [STRT], XSRC, TST
;:CPD_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; DST [NOP], FNC [SUBR], SRC [DA], CIN, CC
; BRT, JA [STRT], XSRC, TST
;:CPR DST [NOP], FNC [SUBR], SRC [AB], CIN, CC
; BRT, JA [STRT], XSRC, TST
;:ADD_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; DST [RAMF], FNC [&ADD], SRC [DA], CC
; BRT, JA [STRT], XSRC, TST
;:ADD DST [RAMF], FNC [&ADD], SRC [AB], CC
; BRT, JA [STRT], XSRC, TST
;:AND_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; DST [RAMF], FNC [&AND], SRC [DA], CC
; BRT, JA [STRT], XSRC, TST
;:AND DST [RAMF], FNC [&AND], SRC [AB], CC
; BRT, JA [STRT], XSRC, TST
;:SUBR DST [RAMF], FNC [RSUB], SRC [AB], CIN, CC
; BRT, JA [STRT], XSRC, TST
;:SUB DST [RAMF], FNC [SUBS], SRC [AB], CIN, CC
; BRT, JA [STRT], XSRC, TST
;:XOR DST [RAMF], FNC [EXOR], SRC [AB], CC
; BRT, JA [STRT], XSRC, TST
;:SSL DST [RAMU], FNC [&ADD], SRC [ZB], CC
; BRT, JA [STRT], XSRC, TST
;:SSLH DST [RAMU], FNC [&ADD], SRC [ZB], SIN, CC
; BRT, JA [STRT], XSRC, TST
;:SSR DST [RAMD], FNC [&ADD], SRC [ZB], CC
; BRT, JA [STRT], XSRC, TST
;:BRC_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0].; BRT, JA [LDPC], XSRC
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; BRT, JA [STRT], XSRC, TST
;:JMP_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
;:LDPC DST [RAMF], FNC [&ADD], SRC [DZ], BR[15], BSRC
; BRT, JA [STRT], XSRC, TST
;:STD_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [MC], DICFC [WA]
; MCPU, FNC [&ADD], SRC [DA], CC
; MCPU, FNC [&ADD], SRC [ZB]
; BRT, JA [STRT], XSRC, TST
;:BAL_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [MC], DICFC [WA]
; MCPU, FNC [&ADD], SRC [ZB], BR [14], BSRC
; MCPU, FNC [&ADD], SRC [ZB], BR [15], BSRC
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR [14], BSRC
; DST [RAMF], FNC [&ADD], SRC [DZ], BR [15], BSRC
; BRT, JA [STRT], XSRC, TST
;:RTN DST [RAMF], FNC [RSUB], SRC [ZB], BR [14], BSRC
; MCPU, DICSRC, DICSC [CM], DICFC [RA]
; MCPU, FNC [&ADD], SRC [ZB], BR [14], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [DZ], BR [15], BSRC
; BRT, JA [STRT], XSRC, TST
;:HIN MCPU, DICSRC, DICSC [CI], DICFC [RA]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [DZ], CC
; BRT, JA [STRT], XSRC, TST
; BRT, JA [STRT], XSRC, TST
;:HOT MCPU, DICSRC, DICSC [OC], DICFC [WA]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, FNC [&ADD], SRC [ZB], CC
; BRT, JA [STRT], XSRC, TST
;:HIN_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [MI], DICFC [RA]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, FNC [&ADD], SRC [ZB]
; BRT, JA [STRT], XSRC, TST
;:HOT_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [OM], DICFC [WA]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, FNC [&ADD], SRC [ZB]
; BRT, JA [STRT], XSRC, TST
;:BIN_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [MI], DICFC [RB]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, FNC [&ADD], SRC [ZB]
; BRT, JA [STRT], XSRC, TST
;:BOT_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [OM], DICFC [WB]
; MCPU, FNC [&ADD], SRC [DZ]
; MCPU, FNC [&ADD], SRC [ZB]
; BRT, JA [STRT], XSRC, TST
;:IOC MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; DST [RAMF], FNC [&ADD], SRC [DZ], BR [13], BSRC
; MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, FNC [&ADD], SRC [ZB], BR [13], BSRC
; MCPU, FNC [&ADD], SRC [DZ]
; BRT, JA [STRT], XSRC, TST
;:HLT MCPU, RST
; BRT, JA [STRT], XSRC, TST
;:LLD_I MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [ZB], BR[15], BSRC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [ZB], CIN, BR[15], BSRC
; MCPU, DICSRC, DICSC [CM]
; MCPU, FNC [&ADD], SRC [DA], CC
; MCPU, DICSRC, DIC [0]
; DST [RAMF], FNC [&ADD], SRC [DZ]
; BRT, JA [STRT], XSRC, TST
; BRT, JA [STRT], XSRC, TST

$PROG_END

$CONT
$CODE
$CONT_END